Senior Verification Engineer

Qualifications

• 7 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
• In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
• Solid understanding of computer architecture
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
• Scripting language such as Python or Perl

Desirable:

• Hands on experience in Formal property verification
• knowledge in high-speed protocols like DDR, PCIe, Ethernet
• Processor based testbenches and emulation